This scheme statistically delivers DC-balance and transitions through the use of a scrambler. Such serializer-plus-8b/10b encoder, and deserializer-plus-decoder blocks are defined in the Gigabit Ethernet specification.Īnother common coding scheme used with SerDes is 64b/66b encoding. The typical 8b/10b SerDes parallel side interfaces have one clock line, one control line and 8 data lines. The control codes allow framing, typically on the start of a packet. The guaranteed transitions allow a receiver to extract the embedded clock. This supports DC-balance, provides framing, and guarantees frequent transitions.
As the clock information is synthesized into the data bit stream, rather than explicitly embedding it, the serializer (transmitter) clock jitter tolerance is to 5–10 ps rms and the reference clock disparity at the deserializer is ☑00 ppm.Ī common coding scheme used with SerDes is 8b/10b encoding.
The deserializer uses the reference clock to monitor the recovered clock from the bit stream.
#Double buffered parallel to serial converter code
5%).Ĩb/10b SerDes maps each data byte to a 10-bit code before serializing the data. As the clock is explicitly embedded and can be recovered from the bit stream, the serializer (transmitter) clock jitter tolerance is relaxed to 80–120 ps rms, while the reference clock disparity at the deserializer can be ±50,000 ppm (i.e. One cycle of clock signal is transmitted first, followed by the data bit stream this creates a periodic rising edge at the start of the data bit stream. The clock jitter tolerance at the serializer is 5–10 ps rms.Īn embedded clock SerDes serializes data and clock into a single stream. The serialized stream is sent along with a reference clock. Parallel clock SerDes is normally used to serialize a parallel bus input along with data address & control signals. The purpose of this encoding/decoding is typically to place at least statistical bounds on the rate of signal transitions to allow for easier clock recovery in the receiver, to provide framing, and to provide DC balance. Some types of SerDes include encoding/decoding blocks. One register is used to clock in the serial stream, and the other is used to hold the data for the slower, parallel side. Implementations typically have two registers connected as a double buffer. The SIPO block then divides the incoming clock down to the parallel rate. However, SerDes which do not transmit a clock use reference clock to lock the PLL to the correct Tx frequency, avoiding low harmonic frequencies present in the data stream. The receive clock may have been recovered from the data by the serial clock recovery technique. The SIPO (Serial Input, Parallel Output) block typically has a receive clock output, a set of data output lines and output data latches. Implementations may also make use of a double-buffered register to avoid metastability when transferring data between clock domains. The simplest form of the PISO has a single shift register that receives the parallel data once per parallel clock, and shifts it out at the higher serial clock rate. It may use an internal or external phase-locked loop (PLL) to multiply the incoming parallel clock up to the serial frequency. The PISO (Parallel Input, Serial Output) block typically has a parallel clock input, a set of data input lines, and input data latches.
There are 4 different SerDes architectures: (1) Parallel clock SerDes, (2) Embedded clock SerDes, (3) 8b/10b SerDes, (4) Bit interleaved SerDes. The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter).
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